// +FHDR------------------------------------------------------------
//                 Copyright (c) 2024 NOVAUTO.
//                       ALL RIGHTS RESERVED
// -----------------------------------------------------------------
// Filename      : axi_flow_cnt.sv
// Author        : ICer
// Created On    : 2024-01-04 17:27
// Last Modified : 2024-01-04 17:52 by ICer
// -----------------------------------------------------------------
// Description:
//
//
// -FHDR------------------------------------------------------------


module axi_flow_cnt #(
    //parameter
  parameter realtime START_TIME = 0ns,
  parameter realtime END_TIME = -1ns, 
  parameter STRB_W  = 16
)( /*AUTOARG*/
   // Inputs
   clk, rst_n, axi_valid, axi_ready, axi_strb
   );

// ----------------------------------------------------------------
// Interface declare
// ----------------------------------------------------------------
input              clk;
input              rst_n;

input              axi_valid;
input              axi_ready;
input [STRB_W -1:0]axi_strb;

// ----------------------------------------------------------------
// Wire declare
// ----------------------------------------------------------------
localparam BIT_W = $clog2(STRB_W*8);

// ----------------------------------------------------------------
// AUTO declare
// ----------------------------------------------------------------
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/

logic [BIT_W -1:0]bit_cnt;
always @* begin
  bit_cnt = {BIT_W{1'b0}};
  for(int i=0; i<STRB_W; i=i+1)begin: BIT_CNT
    if(axi_strb[i] == 1'b1)begin
      bit_cnt = bit_cnt + 1'b1;
    end
  end
end

logic power;
assign power = axi_valid && axi_ready;

flow_cnt
u_flow_cnt(/*AUTOINST*/
           // Inputs
           .clk                         (clk),
           .rst_n                       (rst_n),
           .power                       (power),
           .bit_cnt                     (bit_cnt[BIT_W-1:0]));


endmodule
// Local Variables:
// verilog-auto-inst-param-value:t
// verilog-library-directories:(".")
// verilog-library-extensions:(".v" ".sv")
// End:

